Modem infrared sensors utilise a large number of detector elements to detect radiation and produce an electronic signal from which a thermal image or other information can be obtained. A major problem associated with such multi-element systems is that every element in the detector array has a unique response and offset associated with it, and these must be normalised to some common level for further processing or image display to be performed. Frequently, the response can vary by over 50%, and the offset by several thousand equivalent degrees centigrade, from element to element. In addition, some higher order, non-linear variations between elements are frequently present. The non-uniformity correction processing circuit must be able to cope with these large ranges of transfer without introducing additional noise or distortion into the signal.
Several approaches to correcting detector non-uniformity have been developed over the years. The most obvious approach, frequently used with cooled detector technology such as CMT and InSb materials, has been to digitise the detector output directly to a high resolution, typically 12 to 14 bits. The digital data corresponding to each element is then added to a corresponding offset coefficient and multiplied by a corresponding response coefficient to produce the normalised signal for each element in the array. This can then be further processed for overall offset and gain to produce the thermal image or other signal processing.
One technique developed for uncooled detectors utilises the fact that many such detectors respond only to changes in scene temperature, and therefore the radiation incident on the detector must be interrupted, "chopped", to induce a signal from the detector. Even those detectors which do not require modulation to produce a signal can benefit from employing interruption means, chopper, which provides regular stable referencing for the system. In such systems the signal from each detector can be derived by subtracting the output of each element when viewing the chopper, or reference, from the output produced when viewing the scene. This "image difference processing" (IDP) results in the direct cancellation of individual offset variations between elements, requiring only the correction of response variations from element to element to give a normalised result. Using this IDP process, the period of time when the detector views the chopper or reference is generally known as the "closed" field, while the period of time when the detector views the scene is known as the "open" field. Under normal circumstances, open and closed fields operate sequentially, however in some systems it may only be necessary to view the chopper or scene occasionally, permitting several open fields to occur between successive closed fields or vice versa. The unchopped system is merely the extreme case where many open fields exist and relatively few--perhaps only one during the life of the system--closed fields occur.
Unfortunately, most applications for uncooled detector systems involve man portable operation, where mass and power consumption are at a premium. In addition, uncooled detectors are generally lower cost than their cooled counterparts, and thus the cost of the support electronics represents a higher proportion of the system costs. For these reasons, the direct quantisation of the output from uncooled detectors is generally avoided, since analogue to digital converters with sufficient resolution and bandwidth to do this are both power hungry and expensive. High power consumption also results in increased system mass, due to the increased battery power required, and a consequential increase in operating costs.
Several novel processing architectures have been developed to overcome these problems using lower resolution analogue to digital converters either in tandem or in combination with analogue preprocessing. FIG. 1 shows one such architecture for uncooled detector systems. The output from the detector 1 is first corrected for response via a multiplying digital to analogue converter (MDAC) 2. This is achieved by exposing the detector, normally during manufacture, uniformly at two levels, one of which may be "dark" or chopper, and obtaining from this a multiplication factor for each element by which subsequent values received by the element must be multiplied by MDAC 2 to correct for non-uniformities in response. These multiplication factors are stored in random access memory (RAM) 9. The corrected output value for each element is conveyed to summing amplifier 3, where the outputs of one or more digital to analogue converters (DACs) 4, 5 are subtracted from it. The resultant signal is then digitised, to the level required for display by the analogue to digital converter (ADC) 6.
The contents of offset RAM 7 are updated while the detector 1 is looking at a reference surface, the closed field, and the feedback loop around the DAC 5 and ADC 6 provides stabilisation to drive the input to the ADC 6 to mid range, or zero, during this period. This is achieved by digitising the difference between the DAC 5 and MDAC 2, which contains the response corrected signal, and adding the resultant to the data in the offset RAM 7. Consequently, after the offset RAM 7 has been updated it contains a digital equivalent of the detector response during the closed field, with every location in the RAM 7 corresponding to a unique element in the detector 1. If the loop gain is adjusted to exactly unity, where the LSB of the ADC 6 corresponds to exactly the LSB of the offset DAC 5, then any changes in detector offset are exactly nulled on every update once the loop has converged. During the open field this offset data is again fed to the DAC 5 and hence to the summing amplifier where it is subtracted from the response corrected signal, to generate the IDP data directly. This can then be digitised using the ADC 6 for subsequent processing such as temporal re-sequencing for compatibility with conventional video standards.
A global offset can be added to the signal at the summing amplifier to adjust the thermal window being digitised, thus matching the digitiser range to the thermal scene being observed. In FIG. 1, this global offset is achieved using a DAC 4 to provide the adjustment either manually or under the control of some automatic algorithm integrated in the custom IC 8.
For a thermal imaging sensor typical resolutions for the MDAC 2 and offset DAC 5 are 12 and 16 bits respectively, whilst the ADC 6 can be restricted to the 8 bits normally used for video display systems.
The offset loop is self correcting and changes in offset due to temperature drift or 1/f noise are automatically corrected every time the offset RAM 7 updates during the closed field. During power up, any random data in the offset RAM 7 rapidly converges to the correct values due to the operation of the feedback loop. The rate of convergence to, and subsequent tracking of, the correct offset values is only limited by the dynamic range of the ADC 6 which determines the maximum step between successive updates to the offset data.
This signal processing algorithm and architecture has been successfully applied in low cost thermal imaging sensors based on arrays of 100.times.100 elements.
This approach, although offering the benefits of low cost, volume and power consumption, also has limitations. In particular, the response correction stage (the MDAC) has a limited bandwidth despite consuming a significant proportion of the total power of the analogue circuitry. This is particularly problematic when operating with larger or faster detector arrays where higher bandwidths are required, and is generally overcome by operating multiple analogue processing chains under the supervision of a single digital custom integrated circuit.
In addition, the relative position of the MDAC, 2, and the offset correction DAC, 5, in the processing chain are fixed, since the offset feedback loop must have the same gain for each element in the array to function properly. If the MDAC was placed after the offset correction DAC 5 this loop gain would be different for each element and would introduce image artifacts such as smearing. A consequence of this fixed architecture is that the responsivity correction MDAC 2 compounds the offset range significantly, thus increasing the dynamic range of the offset DAC 5 required.
A further limitation of this approach is the precision of the analogue processing circuits required, which are beyond the capability of current analogue ASIC facilities. Consequently, the analogue processing must be manufactured from commercially available DACs and MDACs, limiting the degree of integration and miniaturisation possible. This restriction limits the minimum costs and volumes achievable, particularly for multiple analogue channel systems.
All of these limitations and restrictions clearly reduce the benefits offered by the processing architecture over the alternative direct digitisation in the first place.
Ideally, the response correction would be implemented in the digital domain, after the signal has been digitised, thus eliminating the MDAC from the circuit and permitting the response matching function to be integrated with the remaining digital processing in ASIC technology. However, the response variations from the detector would then be digitised directly which would significantly limit the scene temperature range for which the system would function. This is shown schematically in FIG. 2, where the input to the ADC is plotted against temperature. The offset correction loop maintains the input to the ADC at zero during the closed field as before, but without the MDAC in the circuit, the response variations remain uncorrected. Consequently, when viewing the infra-red scene, the input to the ADC can be dominated by response variations. Typical response variations of .+-.50% can be present in large arrays of detectors, and elements close to the extreme response ranges saturate the ADC even for small temperature differences from the chopper or reference. The operating range of a system with response variations of .+-.50% is shown in FIG. 2 by the dotted box.
If more extreme temperatures are viewed using a global offset control such as the DAC 4 in FIG. 1, the problem becomes more acute. The output of the DAC effectively shifts the input voltage range of the ADC permitting more extreme voltages, and thus temperatures, to be digitised. Under such circumstances, extreme response elements saturate the ADC and, as the temperature difference from the chopper or reference increases, the outputs of fewer and fewer elements can be digitised. This is shown in FIG. 2 where the offset adjustment results in an ADC input range where saturation of some elements always occurs. For temperatures less than T.sub.2 the lowest response elements saturate negatively, while for temperatures greater than T.sub.1 the high response elements saturate positively. For temperatures between T.sub.1 and T.sub.2 all elements, except those very close to the normalised response, saturate the ADC input.
Hence the responsivity matching must be performed prior to the analogue to digital conversion if saturation problems are to be avoided, and this limitation has prevented the response correction being implemented digitally, despite the potential benefits. EP 0138579 partially addresses the problem of a limited resolution of an A to D converter by adopting a system in which dark field values are subtracted from open field values prior to conversion by the A to D converter. However the resolution available to the open field can still not exceed the resolution of the A to D converter. The present invention aims to overcome this limitation and permit the benefits already mentioned, together with additional functions, to be realised.